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1. general description the cbtl06141 is a six-channel (?hex?) multiplexer for displayport and pci express applications at generation 1 (?gen1?) spe eds. it provides four differential channels capable of 1 : 2 switching or 2 : 1 multiplexing (bidirectional and ac-coupled) pci express or displayport signals, using high-bandwidth pass-gate technology. additionally, it provides for switching/multiple xing of the hot plug detect signal as well as the aux or ddc (direct display control) signals, for a total of six channels on the display side. the aux and ddc channels provide a f our-position multiplexer such that an additional level of multiplexing can be accomplished when aux and ddc i/os are on separate pins of the display source device. the cbtl06141 is designed for gen1 speeds, at 2.5 gbit/s for pci express or 2.7 gbit/s for displayport, and for inputs voltages of up to 3.3 v typical. it consumes very low current in operational mode (less than 1 ma typical) and provides for a shutdown function (less than 10 a) to support battery-powered applications. a typical application of cbtl06141 is on motherboards where one of two gpu display sources needs to be selected to connect to a display sink device or connector. a controller chip selects which path to use by setting a select signal high or low. due to the non-directional nature of the signal paths (which use high-bandwidth passgate technology), the cbtl06141 can also be used in the reverse topology, e.g., to connect one display source device to one of two display sink devices or connectors. optionally, the hex mux device can be used in conjunction with an hdmi/dvi level shifter device (ptn3300a, ptn3300b or ptn3301) to allow for displayport as well as hdmi/dvi connectivity. 2. features and benefits ? 1 : 2 switching or 2 : 1 multiple xing of displayport (v1.1 - 2.7 gbit/s) or pci express (v1.1 - 2.5 gbit/s) signals ? 4 high-speed differential channels with 2 : 1 muxing/switching for displayport or pci express signals ? 1 channel with 4 : 1 muxing/switching for aux differential signals or ddc single-ended clock and data signals ? 1 channel with 2 : 1 muxing/switching for single-ended hpd signals ? high-bandwidth analog pass-gate technology ? very low intra-pair differential skew (< 5 ps) ? very low inter-pair skew (< 180 ps) ? switch/multiplexer posit ion select cmos input ? shutdown mode cmos input cbtl06141 gen1 display 2 : 1 multiplexer rev. 2 ? 15 july 2010 product data sheet
cbtl06141 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 july 2010 2 of 18 nxp semiconductors cbtl06141 gen1 display 2 : 1 multiplexer ? shutdown mode minimizes power consumpt ion while switching all channels off ? ddc and aux ports tolerant to being pulled to +5 v via 2.2 k resistor ? supports hdmi/dvi incorrect dongle connection ? single 3.3 v power supply ? very low operation current of 0.2 ma typical ? very low shutdown current of < 10 a ? esd 8 kv hbm, 1 kv cdm ? esd 2 kv hbm, 500 v cdm for control pins ? available in 5 mm 5 mm, 0.5 mm ball pitch tfbga48 package 3. applications ? motherboard applications requiring displayport and pci express switching/multiplexing ? docking stations ? notebook computers ? chip sets requiring flexible allocation of pci express or displayport i/o pins to board connectors 4. ordering information [1] total height including solder balls af ter printed circuit board mounting = 1.15 mm. table 1. ordering information type number solder process package name description version CBTL06141EE/g pb-free (snagcu solder compound) tfbga48 plastic thin fine-pitch ball grid array package; 48 balls; body 5 5 0.8 mm [1] sot918-1
cbtl06141 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 july 2010 3 of 18 nxp semiconductors cbtl06141 gen1 display 2 : 1 multiplexer 5. functional diagram fig 1. functional diagram cbtl06141 vdd din1_n+ dout_n ? aux+ aux ? 0 1 aux+ or scl dout_n+ din1_n ? 002aad554 din2_n+ din2_n ? 4 4 4 daux1+ 00 10 daux1 ? daux2+ daux2 ? 01 ddc_clk1 ddc_dat1 11 ddc_clk2 ddc_dat2 0 1 hpd_1 hpd_2 gpu_sel ddc_aux_sel tst0 xsd aux ? or sda hpdin gnd
cbtl06141 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 july 2010 4 of 18 nxp semiconductors cbtl06141 gen1 display 2 : 1 multiplexer 6. pinning information 6.1 pinning fig 2. pin configuration for tfbga48 transparent top view fig 3. ball mapping 002aad36 0 transparent top view CBTL06141EE/g h j g f e d c a b 24689 1357 ball a1 index area 1 a 002aad36 1 gpu_sel vdd din1_0 ? din1_1 ? din1_2 ? din1_3+ din1_3 ? 23456789 b dout_0 ? dout_0+ gnd din1_0+ din1_1+ din1_2+ xsd din2_0+ din2_0 ? c ddc_aux _sel gnd d dout_1 ? dout_1+ din2_1+ din2_1 ? e dout_2 ? dout_2+ din2_2+ din2_2 ? f dout_3 ? dout_3+ din2_3+ din2_3 ? g tst0 gnd h aux ? aux+ hpd_2 gnd ddc_clk2 daux2+ gnd ddc_clk1 daux1+ j hpdin hpd_1 vdd ddc_dat2 daux2 ? ddc_dat1 daux1 ?
cbtl06141 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 july 2010 5 of 18 nxp semiconductors cbtl06141 gen1 display 2 : 1 multiplexer 6.2 pin description table 2. pin description symbol ball type description gpu_sel a1 3.3 v low-voltage cmos single-ended input selects between two mu ltiplexer/switch path s. when high, path 2 left-side is connected to its corresponding right-side i/o. when low, path 1 left-side is connected to its corresponding right-side i/o. ddc_aux_sel c2 3.3 v low-voltage cmos single-ended input selects between ddc and aux paths. when high, the clk and dat i/os are connected to their respective ddcout terminals. when low, the aux+ and aux ? i/os are connected to their respective ddcout terminals. xsd b7 3.3 v low-voltage cmos single-ended input shutdown pin. should be driven high or connected to vdd for normal operation. when low, all paths are switched off (non-conducting) and supply current consumption is minimized. tst0 g2 3.3 v low-voltage cmos single-ended input test pin for nxp use only. should be tied to ground in normal operation. din1_0+ b4 differential i/o four high-speed differential pairs for displayport or pci express signals, path 1, left-side. din1_0 ? a4 differential i/o din1_1+ b5 differential i/o din1_1 ? a5 differential i/o din1_2+ b6 differential i/o din1_2 ? a6 differential i/o din1_3+ a8 differential i/o din1_3 ? a9 differential i/o din2_0+ b8 differential i/o four high-speed differential pairs for displayport or pci express signals, path 2, left-side. din2_0 ? b9 differential i/o din2_1+ d8 differential i/o din2_1 ? d9 differential i/o din2_2+ e8 differential i/o din2_2 ? e9 differential i/o din2_3+ f8 differential i/o din2_3 ? f9 differential i/o dout_0+ b2 differential i/o four high-speed differential pairs for displayport or pci express signals, right-side. dout_0 ? b1 differential i/o dout_1+ d2 differential i/o dout_1 ? d1 differential i/o dout_2+ e2 differential i/o dout_2 ? e1 differential i/o dout_3+ f2 differential i/o dout_3 ? f1 differential i/o daux1+ h9 differential i/o high-speed differential pair for aux signals, path 1, left-side. daux1 ? j9 differential i/o daux2+ h6 differential i/o high-speed differential pair for aux signals, path 2, left-side. daux2 ? j6 differential i/o
cbtl06141 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 july 2010 6 of 18 nxp semiconductors cbtl06141 gen1 display 2 : 1 multiplexer 7. functional description refer to figure 1 ? functional diagram ? . the cbtl06141 uses a 3.3 v power supply. all main signal paths are implemented using high-bandwidth pass-gate technology and are non-directional. no clock or reset signal is needed for the multiplexer to function. the switch position for the main channels is selected using the select signal gpu_sel. additionally, the signal ddc_aux_sel select s between aux and ddc positions for the ddc / aux channel. the detailed operation is described in section 7.1 . 7.1 multiplexer/switc h select functions the internal multiplexer swit ch position is controlled by two logic inputs gpu_sel and ddc_aux_sel as described below. ddc_clk1 h8 differential i/o pair of single-ended terminals for ddc clock and data signals, path 1, left-side. ddc_dat1 j8 differential i/o ddc_clk2 h5 differential i/o pair of single-ended terminals for ddc clock and data signals, path 2, left-side. ddc_dat2 j5 differential i/o aux+ h2 differential i/o high-speed differential pair for aux or single-ended ddc signals, right-side. aux ? h1 differential i/o hpd_1 j2 single-ended i/o single ended channel for the hpd signal, path 1, left-side. hpd_2 h3 single-ended i/o single ended channel for the hpd signal, path 2, left-side. hpdin j1 single-ended i/o single ended channel for the hpd signal, right-side. vdd a2, j4 power supply 3.3 v power supply. gnd b3, c8, g8, h4, h7 ground ground. table 2. pin description ?continued symbol ball type description table 3. multiplexer/switch select control for din and dout channels gpu_sel din1_n din2_n 0 active; connected to dout_n high-impedance 1 high-impedance active; connected to dout_n table 4. multiplexer/switch sele ct control for hpd channel gpu_sel hpd1 hpd2 0 active; connected to hpdin high-impedance 1 high-impedance active; connected to hpdin
cbtl06141 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 july 2010 7 of 18 nxp semiconductors cbtl06141 gen1 display 2 : 1 multiplexer 7.2 shutdown function the cbtl06141 provides a shutdown function to minimize power consumption when the application is not active but power to the cbtl06141 is provided. pin xsd (active low) puts all channels in off mode (non-conducting) while reducing current consumption to near-zero. table 5. multiplexer/switch select control for ddc and aux channels ddc_aux_sel gpu_sel daux1 daux2 ddc_clk1, ddc_dat1 ddc_clk2, ddc_dat2 0 0 active; connected to aux high-impedance high-impedance high-impedance 0 1 high-impedance active; connected to aux high-impedance high-impedance 1 0 high-impedance hig h-impedance active; connected to aux high-impedance 1 1 high-impedance high-imped ance high-impedance active; connected to aux table 6. shutdown function xsd state 0 shutdown 1active
cbtl06141 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 july 2010 8 of 18 nxp semiconductors cbtl06141 gen1 display 2 : 1 multiplexer 8. limiting values [1] human body model: ansi/eos/esd-s5.1-1994, standard for esd sensitivity testing, human body model - component level; electrostatic disc harge association, rome, ny, usa. [2] charged-device model: ansi/eos/esd-s5.3-1- 1999, standard for esd sensitivity testing, charged-device model - component level; electr ostatic discharge association, rome, ny, usa. 9. recommended operating conditions [1] hpd input is tolerant to 5 v input, provided a 1 k series resistor between the voltage source and the pin is placed in series. see section 11.1 ? special considerations ? . table 7. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.3 +5 v t case case temperature ? 40 +85 c v esd electrostatic discharge voltage hbm [1] - 8000 v hbm; cmos inputs [1] - 2000 v cdm [2] - 1000 v cdm; cmos inputs [2] 500 v table 8. recommended operating conditions symbol parameter conditions min typ max unit v dd supply voltage 3.0 3.3 3.6 v v i input voltage cmos inputs ? 0.3 - v dd +0.3 v other inputs ? 0.3 - +2.6 v hpd, ddc inputs [1] ? 0.3 - v dd +0.3 v t amb ambient temperature oper ating in free air ? 10 - +85 c
cbtl06141 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 july 2010 9 of 18 nxp semiconductors cbtl06141 gen1 display 2 : 1 multiplexer 10. characteristics 10.1 general characteristics 10.2 displayport channel characteristics table 9. general characteristics symbol parameter conditions min typ max unit i dd supply current operating mode (xsd = high); v dd =3.3v - 0.2 1 ma shutdown mode (xsd = low); v dd =3.3v--10 a p cons power consumption operating mode (xsd = high); v dd =3.3v--5mw t startup start-up time supply voltage valid or xsd going high to channel specified operating characteristics --1ms t rcfg reconfiguration time gpu_sel or ddc_aux_sel state change to channel specified operating characteristics --1ms table 10. displayport channel characteristics symbol parameter conditions min typ max unit v i input voltage ? 0.3 - +2.6 v v ic common-mode input voltage 0 - 2.0 v v id differential input voltage ? 1.2 - +1.2 v ddil differential insertion loss channel is on; 0 hz f 1.0 ghz ? 2.5 ? 1.6 - db channel is on; f = 2.5 ghz ? 4.5--db channel is off; 0 hz f 3.0 ghz - - ? 20 db ddrl differential return loss channel is on; 0 hz f 1.0 ghz - - ? 10 db ddnext differential near-end crosstalk adjacent channels are on; 0hz f 1.0 ghz -- ? 30 db b bandwidth ? 3.0 db intercept - 2.5 - ghz ? 5.0 db intercept - 4.0 - ghz t pd propagation delay from left-side port to right-side port or vice versa -180-ps t sk(dif) differential skew time intra-pair - - 5 ps t sk skew time inter-pair - - 180 ps
cbtl06141 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 july 2010 10 of 18 nxp semiconductors cbtl06141 gen1 display 2 : 1 multiplexer 10.3 aux and ddc ports [1] time from ddc/aux input changing state to aux output changing state. includes ddc/aux rise/fall time. 10.4 hpdin input , hpd_x outputs [1] voltage measured at hpd_1 or hpd_2 with i nput voltage applied to hpdin, or vice versa. [2] time from hpdin changing state to hpd_x changing state. includes hpd rise/fall time. 10.5 gpu_sel, ddc_aux_sel and xsd inputs table 11. aux and ddc port characteristics symbol parameter conditions min typ max unit v i input voltage no series resistor ? 0.3 - v dd +0.3 v 2.2 k series resistor ? 0.3 - +5.0 v v o output voltage no series resistor; v i = 3.6 v 3.0 - 3.6 v 2.2 k series resistor; v i = 5.0 v 3.0 - 4.3 v v ic common-mode input voltage ddc or aux 0 - 2.0 v v id differential input voltage ? 1.2 - +1.2 v t pd propagation delay from left-side port to right-side port or vice versa [1] - 180 - ps table 12. hpd input and output characteristics symbol parameter conditions min typ max unit v i input voltage no series resistor ? 0.3 - v dd +0.3 v 1k series resistor [1] ? 0.3 - +5.0 v v o output voltage no series resistor; v i = 3.6 v 3.0 - 3.6 v 1k series resistor; v i = 5.0 v 3.0 - 4.3 v t pd propagation delay from hpdin to hpd_x or vice versa [2] -180- ps table 13. gpu_sel, ddc_aux_sel, xsd input characteristics symbol parameter conditions min typ max unit v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v i li input leakage current v dd =3.6v; 0.3v v i 3.9 v - - 10 a
cbtl06141 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 july 2010 11 of 18 nxp semiconductors cbtl06141 gen1 display 2 : 1 multiplexer 11. application information 11.1 special considerations certain cable or dongle misplug scenarios make it possible for a 5 v input condition to occur on pins aux+ and aux ? , as well as hpdin. when aux+ and aux ? are connected through a minimum of 2.2 k each, the cbtl06141 will si nk current but will not be damaged. similarly, hpdin may be c onnected to 5 v via at least a 1 k resistor. (correct functional operation to specification is not expected in these scenarios.) the latter also prevents the hpdin input from loading down the system hpd signal when power to the cbtl06141 is off.
cbtl06141 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 july 2010 12 of 18 nxp semiconductors cbtl06141 gen1 display 2 : 1 multiplexer 12. package outline fig 4. package outline tfbga48 (sot918-1) references outline version european projection issue date iec jedec jeita sot918-1 mo-195 - - - - - - sot918- 1 05-09-21 05-10-13 unit a max mm 1.15 0.25 0.15 0.90 0.75 0.35 0.25 5.1 4.9 5.1 4.9 a 1 dimensions (mm are the original dimensions) t fbga48: plastic thin fine-pitch ball grid array package; 48 balls; body 5 x 5 x 0.8 mm x a 2 b d e e 2 4 e 1 4 e 0.5 v 0.15 w 0.05 y 0.08 y 1 0.1 0 2.5 5 mm scale b ball a1 index area a b c d e f h g j 2468 13579 e 2 e 1 e e a c b ? v m c ? w m ball a1 index area b a e d c y c y 1 detail x a a 1 a 2
cbtl06141 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 july 2010 13 of 18 nxp semiconductors cbtl06141 gen1 display 2 : 1 multiplexer 13. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
cbtl06141 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 july 2010 14 of 18 nxp semiconductors cbtl06141 gen1 display 2 : 1 multiplexer 13.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 5 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 4 and 15 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 5 . table 14. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 15. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
cbtl06141 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 july 2010 15 of 18 nxp semiconductors cbtl06141 gen1 display 2 : 1 multiplexer for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 14. abbreviations 15. revision history msl: moisture sensitivity level fig 5. temperature profiles for large and small components 001aac84 4 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 16. abbreviations acronym description ddc direct display control dut device under test dvi digital video interface hdmi high-definition multimedia interface pcb printed-circuit board sma subminiature, version a (connector) tdr time-domain reflectometry aux auxiliary channel (in displayport definition) hpd hot plug detect gpu graphics processor unit pcie pci express table 17. revision history document id release date data sheet status change notice supersedes cbtl06141 v.2 20100715 product data sheet - cbtl06141 v.1 modifications: ? removed ?company confidential? watermark cbtl06141 v.1 20080624 product data sheet - -
cbtl06141 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 july 2010 16 of 18 nxp semiconductors cbtl06141 gen1 display 2 : 1 multiplexer 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 16.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 16.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
cbtl06141 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 15 july 2010 17 of 18 nxp semiconductors cbtl06141 gen1 display 2 : 1 multiplexer non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 16.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 17. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors cbtl06141 gen1 display 2 : 1 multiplexer ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 15 july 2010 document identifier: cbtl06141 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 multiplexer/switch select functions . . . . . . . . . . 6 7.2 shutdown function . . . . . . . . . . . . . . . . . . . . . . 7 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 recommended operating conditions. . . . . . . . 8 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 10.1 general characteristics . . . . . . . . . . . . . . . . . . . 9 10.2 displayport channel characteristics . . . . . . . . . 9 10.3 aux and ddc ports . . . . . . . . . . . . . . . . . . . . 10 10.4 hpdin input, hpd_x outputs . . . . . . . . . . . . . 10 10.5 gpu_sel, d dc_aux_sel and xsd inputs . 10 11 application information. . . . . . . . . . . . . . . . . . 11 11.1 special considerations . . . . . . . . . . . . . . . . . . 11 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 13 soldering of smd packages . . . . . . . . . . . . . . 13 13.1 introduction to soldering . . . . . . . . . . . . . . . . . 13 13.2 wave and reflow soldering . . . . . . . . . . . . . . . 13 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 13 13.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 14 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 16 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 16.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 contact information. . . . . . . . . . . . . . . . . . . . . 17 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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